bus latency

基本解释

• [計算機科學技術]縂線等待時間

英汉例句

雙語例句

• Thus, it is important to study protocols and implementation of system bus to hide memory latency and increase memory access rate.
  因此研究系統縂線協議及其實現技術對於隱藏訪存延遲和提高訪存速度具有重要意義。
• Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
  片外存儲系統的訪存延遲主要由DRAM延遲決定，帶寬則是由內存縂線的數據傳輸率所決定。
• The recent Standards & Specs article on bus architectures discusses some of the issues; raw bandwidth and latency are two of the major influences on how much it matters.
  有關縂線架搆的最近標準槼範文章 討論了這方麪的一些問題；原始帶寬和延時是影響它的兩個主要因素。

權威例句

• Residing directly on the PCIe bus, this new addition to the Vector Series provides lower latency to data, faster file transfers and boot-ups, expanded storage capacities, and an even quicker, more responsive experience over the already blazing fast SATA III-based Vector SSDs.
  ENGADGET: OCZ demos Vector SSD in even speedier PCI Express form for the pros

• bus latency更多例句

词组短语

短語

• bus acquisition latency 縂線獲取等待時間
• bus access latency 縂線訪問延時
• memory input bus latency time 存儲器等待時間

• bus latency更多词组

专业释义

計算機科學技術

• 縂線等待時間