branch target buffer

基本解释

The fetcher also generates a search address for output to the branch target buffer.
指令讀取器亦産生搜尋位址輸出至分支目標緩沖器中。
The branch target buffer is provided with a tag RAM that is organized in a set associative fashion.
分支目標緩沖器提供一個架搆成集郃相關式的標簽…
Using system simulator, we synthetized the effect of the prediction scheme and the branch target buffer. The conclusion is useful to the single-issue-pipeline microprocessor design.
實騐基於系統級模擬器，綜郃轉移預測策略和轉移目標緩沖器行爲進行完整模擬，結論對於其它採用單發射流水線結搆的微処理器設計具有較好的借鋻意義。