combinational circuit

常见例句

The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。
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A combinational circuit that has three inputs that are an augend , D, an addend, E, and carry digit transferred from another digit place, F, and two outputs that are a '.
三个输入端是：被加数d、加数e以及从另一个数位传来的进位数f；两个输出端是：无进位和数t及新的进位数r。
Results indicate that when fault duration is shorter than phase difference of three clocks, enhanced ST-TMR can almost mask the SEU in combinational logic circuit and clock line.
故障注入的结果显示，时空三模冗余技术在故障持续时间不大于三路时钟的相位差的情况下，可以很好的屏蔽组合逻辑和时钟线的单粒子翻转（SEU）事件。